
rtc-compare:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400648 <_init>:
  400648:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  40064c:	910003fd 	mov	x29, sp
  400650:	9400004a 	bl	400778 <call_weak_fn>
  400654:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400658:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400660 <.plt>:
  400660:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400664:	b0000090 	adrp	x16, 411000 <__FRAME_END__+0x101fc>
  400668:	f947fe11 	ldr	x17, [x16, #4088]
  40066c:	913fe210 	add	x16, x16, #0xff8
  400670:	d61f0220 	br	x17
  400674:	d503201f 	nop
  400678:	d503201f 	nop
  40067c:	d503201f 	nop

0000000000400680 <exit@plt>:
  400680:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400684:	f9400211 	ldr	x17, [x16]
  400688:	91000210 	add	x16, x16, #0x0
  40068c:	d61f0220 	br	x17

0000000000400690 <open@plt>:
  400690:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400694:	f9400611 	ldr	x17, [x16, #8]
  400698:	91002210 	add	x16, x16, #0x8
  40069c:	d61f0220 	br	x17

00000000004006a0 <__libc_start_main@plt>:
  4006a0:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  4006a4:	f9400a11 	ldr	x17, [x16, #16]
  4006a8:	91004210 	add	x16, x16, #0x10
  4006ac:	d61f0220 	br	x17

00000000004006b0 <memset@plt>:
  4006b0:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  4006b4:	f9400e11 	ldr	x17, [x16, #24]
  4006b8:	91006210 	add	x16, x16, #0x18
  4006bc:	d61f0220 	br	x17

00000000004006c0 <close@plt>:
  4006c0:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  4006c4:	f9401211 	ldr	x17, [x16, #32]
  4006c8:	91008210 	add	x16, x16, #0x20
  4006cc:	d61f0220 	br	x17

00000000004006d0 <__gmon_start__@plt>:
  4006d0:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  4006d4:	f9401611 	ldr	x17, [x16, #40]
  4006d8:	9100a210 	add	x16, x16, #0x28
  4006dc:	d61f0220 	br	x17

00000000004006e0 <abort@plt>:
  4006e0:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  4006e4:	f9401a11 	ldr	x17, [x16, #48]
  4006e8:	9100c210 	add	x16, x16, #0x30
  4006ec:	d61f0220 	br	x17

00000000004006f0 <puts@plt>:
  4006f0:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  4006f4:	f9401e11 	ldr	x17, [x16, #56]
  4006f8:	9100e210 	add	x16, x16, #0x38
  4006fc:	d61f0220 	br	x17

0000000000400700 <strcmp@plt>:
  400700:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400704:	f9402211 	ldr	x17, [x16, #64]
  400708:	91010210 	add	x16, x16, #0x40
  40070c:	d61f0220 	br	x17

0000000000400710 <printf@plt>:
  400710:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400714:	f9402611 	ldr	x17, [x16, #72]
  400718:	91012210 	add	x16, x16, #0x48
  40071c:	d61f0220 	br	x17

0000000000400720 <ioctl@plt>:
  400720:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400724:	f9402a11 	ldr	x17, [x16, #80]
  400728:	91014210 	add	x16, x16, #0x50
  40072c:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400730 <_start>:
  400730:	d280001d 	mov	x29, #0x0                   	// #0
  400734:	d280001e 	mov	x30, #0x0                   	// #0
  400738:	aa0003e5 	mov	x5, x0
  40073c:	f94003e1 	ldr	x1, [sp]
  400740:	910023e2 	add	x2, sp, #0x8
  400744:	910003e6 	mov	x6, sp
  400748:	580000c0 	ldr	x0, 400760 <_start+0x30>
  40074c:	580000e3 	ldr	x3, 400768 <_start+0x38>
  400750:	58000104 	ldr	x4, 400770 <_start+0x40>
  400754:	97ffffd3 	bl	4006a0 <__libc_start_main@plt>
  400758:	97ffffe2 	bl	4006e0 <abort@plt>
  40075c:	00000000 	.inst	0x00000000 ; undefined
  400760:	004009dc 	.word	0x004009dc
  400764:	00000000 	.word	0x00000000
  400768:	00400bf0 	.word	0x00400bf0
  40076c:	00000000 	.word	0x00000000
  400770:	00400c70 	.word	0x00400c70
  400774:	00000000 	.word	0x00000000

0000000000400778 <call_weak_fn>:
  400778:	b0000080 	adrp	x0, 411000 <__FRAME_END__+0x101fc>
  40077c:	f947f000 	ldr	x0, [x0, #4064]
  400780:	b4000040 	cbz	x0, 400788 <call_weak_fn+0x10>
  400784:	17ffffd3 	b	4006d0 <__gmon_start__@plt>
  400788:	d65f03c0 	ret
  40078c:	00000000 	.inst	0x00000000 ; undefined

0000000000400790 <deregister_tm_clones>:
  400790:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400794:	9101a000 	add	x0, x0, #0x68
  400798:	d0000081 	adrp	x1, 412000 <exit@GLIBC_2.17>
  40079c:	9101a021 	add	x1, x1, #0x68
  4007a0:	eb00003f 	cmp	x1, x0
  4007a4:	540000a0 	b.eq	4007b8 <deregister_tm_clones+0x28>  // b.none
  4007a8:	90000001 	adrp	x1, 400000 <_init-0x648>
  4007ac:	f9464821 	ldr	x1, [x1, #3216]
  4007b0:	b4000041 	cbz	x1, 4007b8 <deregister_tm_clones+0x28>
  4007b4:	d61f0020 	br	x1
  4007b8:	d65f03c0 	ret
  4007bc:	d503201f 	nop

00000000004007c0 <register_tm_clones>:
  4007c0:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  4007c4:	9101a000 	add	x0, x0, #0x68
  4007c8:	d0000081 	adrp	x1, 412000 <exit@GLIBC_2.17>
  4007cc:	9101a021 	add	x1, x1, #0x68
  4007d0:	cb000021 	sub	x1, x1, x0
  4007d4:	9343fc21 	asr	x1, x1, #3
  4007d8:	8b41fc21 	add	x1, x1, x1, lsr #63
  4007dc:	9341fc21 	asr	x1, x1, #1
  4007e0:	b40000a1 	cbz	x1, 4007f4 <register_tm_clones+0x34>
  4007e4:	90000002 	adrp	x2, 400000 <_init-0x648>
  4007e8:	f9464c42 	ldr	x2, [x2, #3224]
  4007ec:	b4000042 	cbz	x2, 4007f4 <register_tm_clones+0x34>
  4007f0:	d61f0040 	br	x2
  4007f4:	d65f03c0 	ret

00000000004007f8 <__do_global_dtors_aux>:
  4007f8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4007fc:	910003fd 	mov	x29, sp
  400800:	f9000bf3 	str	x19, [sp, #16]
  400804:	d0000093 	adrp	x19, 412000 <exit@GLIBC_2.17>
  400808:	3941a260 	ldrb	w0, [x19, #104]
  40080c:	35000080 	cbnz	w0, 40081c <__do_global_dtors_aux+0x24>
  400810:	97ffffe0 	bl	400790 <deregister_tm_clones>
  400814:	52800020 	mov	w0, #0x1                   	// #1
  400818:	3901a260 	strb	w0, [x19, #104]
  40081c:	f9400bf3 	ldr	x19, [sp, #16]
  400820:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400824:	d65f03c0 	ret

0000000000400828 <frame_dummy>:
  400828:	17ffffe6 	b	4007c0 <register_tm_clones>

000000000040082c <rtc_main>:
  40082c:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400830:	910003fd 	mov	x29, sp
  400834:	12800000 	mov	w0, #0xffffffff            	// #-1
  400838:	b9003fa0 	str	w0, [x29, #60]
  40083c:	12800000 	mov	w0, #0xffffffff            	// #-1
  400840:	b9003ba0 	str	w0, [x29, #56]
  400844:	90000000 	adrp	x0, 400000 <_init-0x648>
  400848:	91328000 	add	x0, x0, #0xca0
  40084c:	f9001ba0 	str	x0, [x29, #48]
  400850:	52800041 	mov	w1, #0x2                   	// #2
  400854:	f9401ba0 	ldr	x0, [x29, #48]
  400858:	97ffff8e 	bl	400690 <open@plt>
  40085c:	b9003ba0 	str	w0, [x29, #56]
  400860:	b9403ba0 	ldr	w0, [x29, #56]
  400864:	7100001f 	cmp	w0, #0x0
  400868:	540000ea 	b.ge	400884 <rtc_main+0x58>  // b.tcont
  40086c:	90000000 	adrp	x0, 400000 <_init-0x648>
  400870:	9132c000 	add	x0, x0, #0xcb0
  400874:	f9401ba1 	ldr	x1, [x29, #48]
  400878:	97ffffa6 	bl	400710 <printf@plt>
  40087c:	12800000 	mov	w0, #0xffffffff            	// #-1
  400880:	1400001f 	b	4008fc <rtc_main+0xd0>
  400884:	910043a0 	add	x0, x29, #0x10
  400888:	d2800382 	mov	x2, #0x1c                  	// #28
  40088c:	52800001 	mov	w1, #0x0                   	// #0
  400890:	97ffff88 	bl	4006b0 <memset@plt>
  400894:	5280fc00 	mov	w0, #0x7e0                 	// #2016
  400898:	b90013a0 	str	w0, [x29, #16]
  40089c:	52800120 	mov	w0, #0x9                   	// #9
  4008a0:	b90017a0 	str	w0, [x29, #20]
  4008a4:	52800240 	mov	w0, #0x12                  	// #18
  4008a8:	b9001ba0 	str	w0, [x29, #24]
  4008ac:	52800120 	mov	w0, #0x9                   	// #9
  4008b0:	b9001fa0 	str	w0, [x29, #28]
  4008b4:	b90023bf 	str	wzr, [x29, #32]
  4008b8:	b90027bf 	str	wzr, [x29, #36]
  4008bc:	910043a0 	add	x0, x29, #0x10
  4008c0:	aa0003e2 	mov	x2, x0
  4008c4:	d28e0141 	mov	x1, #0x700a                	// #28682
  4008c8:	f2a80381 	movk	x1, #0x401c, lsl #16
  4008cc:	b9403ba0 	ldr	w0, [x29, #56]
  4008d0:	97ffff94 	bl	400720 <ioctl@plt>
  4008d4:	b9003fa0 	str	w0, [x29, #60]
  4008d8:	b9403fa0 	ldr	w0, [x29, #60]
  4008dc:	7100001f 	cmp	w0, #0x0
  4008e0:	5400008a 	b.ge	4008f0 <rtc_main+0xc4>  // b.tcont
  4008e4:	90000000 	adrp	x0, 400000 <_init-0x648>
  4008e8:	91330000 	add	x0, x0, #0xcc0
  4008ec:	97ffff81 	bl	4006f0 <puts@plt>
  4008f0:	b9403ba0 	ldr	w0, [x29, #56]
  4008f4:	97ffff73 	bl	4006c0 <close@plt>
  4008f8:	52800000 	mov	w0, #0x0                   	// #0
  4008fc:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400900:	d65f03c0 	ret

0000000000400904 <ds3231_main>:
  400904:	a9ba7bfd 	stp	x29, x30, [sp, #-96]!
  400908:	910003fd 	mov	x29, sp
  40090c:	12800000 	mov	w0, #0xffffffff            	// #-1
  400910:	b9005fa0 	str	w0, [x29, #92]
  400914:	12800000 	mov	w0, #0xffffffff            	// #-1
  400918:	b9005ba0 	str	w0, [x29, #88]
  40091c:	90000000 	adrp	x0, 400000 <_init-0x648>
  400920:	91338000 	add	x0, x0, #0xce0
  400924:	f9002ba0 	str	x0, [x29, #80]
  400928:	52800041 	mov	w1, #0x2                   	// #2
  40092c:	f9402ba0 	ldr	x0, [x29, #80]
  400930:	97ffff58 	bl	400690 <open@plt>
  400934:	b9005ba0 	str	w0, [x29, #88]
  400938:	b9405ba0 	ldr	w0, [x29, #88]
  40093c:	7100001f 	cmp	w0, #0x0
  400940:	540000ea 	b.ge	40095c <ds3231_main+0x58>  // b.tcont
  400944:	90000000 	adrp	x0, 400000 <_init-0x648>
  400948:	9132c000 	add	x0, x0, #0xcb0
  40094c:	f9402ba1 	ldr	x1, [x29, #80]
  400950:	97ffff70 	bl	400710 <printf@plt>
  400954:	12800000 	mov	w0, #0xffffffff            	// #-1
  400958:	1400001f 	b	4009d4 <ds3231_main+0xd0>
  40095c:	910063a0 	add	x0, x29, #0x18
  400960:	d2800702 	mov	x2, #0x38                  	// #56
  400964:	52800001 	mov	w1, #0x0                   	// #0
  400968:	97ffff52 	bl	4006b0 <memset@plt>
  40096c:	5280fc00 	mov	w0, #0x7e0                 	// #2016
  400970:	b9002fa0 	str	w0, [x29, #44]
  400974:	52800120 	mov	w0, #0x9                   	// #9
  400978:	b9002ba0 	str	w0, [x29, #40]
  40097c:	52800240 	mov	w0, #0x12                  	// #18
  400980:	b90027a0 	str	w0, [x29, #36]
  400984:	52800120 	mov	w0, #0x9                   	// #9
  400988:	b90023a0 	str	w0, [x29, #32]
  40098c:	b9001fbf 	str	wzr, [x29, #28]
  400990:	b9001bbf 	str	wzr, [x29, #24]
  400994:	910063a0 	add	x0, x29, #0x18
  400998:	aa0003e2 	mov	x2, x0
  40099c:	d28e0141 	mov	x1, #0x700a                	// #28682
  4009a0:	f2a80481 	movk	x1, #0x4024, lsl #16
  4009a4:	b9405ba0 	ldr	w0, [x29, #88]
  4009a8:	97ffff5e 	bl	400720 <ioctl@plt>
  4009ac:	b9005fa0 	str	w0, [x29, #92]
  4009b0:	b9405fa0 	ldr	w0, [x29, #92]
  4009b4:	7100001f 	cmp	w0, #0x0
  4009b8:	5400008a 	b.ge	4009c8 <ds3231_main+0xc4>  // b.tcont
  4009bc:	90000000 	adrp	x0, 400000 <_init-0x648>
  4009c0:	9133c000 	add	x0, x0, #0xcf0
  4009c4:	97ffff4b 	bl	4006f0 <puts@plt>
  4009c8:	b9405ba0 	ldr	w0, [x29, #88]
  4009cc:	97ffff3d 	bl	4006c0 <close@plt>
  4009d0:	52800000 	mov	w0, #0x0                   	// #0
  4009d4:	a8c67bfd 	ldp	x29, x30, [sp], #96
  4009d8:	d65f03c0 	ret

00000000004009dc <main>:
  4009dc:	a9b77bfd 	stp	x29, x30, [sp, #-144]!
  4009e0:	910003fd 	mov	x29, sp
  4009e4:	b9001fa0 	str	w0, [x29, #28]
  4009e8:	f9000ba1 	str	x1, [x29, #16]
  4009ec:	12800000 	mov	w0, #0xffffffff            	// #-1
  4009f0:	b9008fa0 	str	w0, [x29, #140]
  4009f4:	b9401fa0 	ldr	w0, [x29, #28]
  4009f8:	7100041f 	cmp	w0, #0x1
  4009fc:	5400010c 	b.gt	400a1c <main+0x40>
  400a00:	f9400ba0 	ldr	x0, [x29, #16]
  400a04:	f9400001 	ldr	x1, [x0]
  400a08:	90000000 	adrp	x0, 400000 <_init-0x648>
  400a0c:	91346000 	add	x0, x0, #0xd18
  400a10:	97ffff40 	bl	400710 <printf@plt>
  400a14:	52800000 	mov	w0, #0x0                   	// #0
  400a18:	97ffff1a 	bl	400680 <exit@plt>
  400a1c:	9101a3a0 	add	x0, x29, #0x68
  400a20:	d2800382 	mov	x2, #0x1c                  	// #28
  400a24:	52800001 	mov	w1, #0x0                   	// #0
  400a28:	97ffff22 	bl	4006b0 <memset@plt>
  400a2c:	f9400ba0 	ldr	x0, [x29, #16]
  400a30:	91002000 	add	x0, x0, #0x8
  400a34:	f9400002 	ldr	x2, [x0]
  400a38:	90000000 	adrp	x0, 400000 <_init-0x648>
  400a3c:	91352000 	add	x0, x0, #0xd48
  400a40:	aa0003e1 	mov	x1, x0
  400a44:	aa0203e0 	mov	x0, x2
  400a48:	97ffff2e 	bl	400700 <strcmp@plt>
  400a4c:	7100001f 	cmp	w0, #0x0
  400a50:	54000081 	b.ne	400a60 <main+0x84>  // b.any
  400a54:	97ffff76 	bl	40082c <rtc_main>
  400a58:	97ffffab 	bl	400904 <ds3231_main>
  400a5c:	14000062 	b	400be4 <main+0x208>
  400a60:	f9400ba0 	ldr	x0, [x29, #16]
  400a64:	91002000 	add	x0, x0, #0x8
  400a68:	f9400002 	ldr	x2, [x0]
  400a6c:	90000000 	adrp	x0, 400000 <_init-0x648>
  400a70:	91354000 	add	x0, x0, #0xd50
  400a74:	aa0003e1 	mov	x1, x0
  400a78:	aa0203e0 	mov	x0, x2
  400a7c:	97ffff21 	bl	400700 <strcmp@plt>
  400a80:	7100001f 	cmp	w0, #0x0
  400a84:	54000a61 	b.ne	400bd0 <main+0x1f4>  // b.any
  400a88:	90000000 	adrp	x0, 400000 <_init-0x648>
  400a8c:	91328000 	add	x0, x0, #0xca0
  400a90:	52800041 	mov	w1, #0x2                   	// #2
  400a94:	97fffeff 	bl	400690 <open@plt>
  400a98:	b9008ba0 	str	w0, [x29, #136]
  400a9c:	b9408ba0 	ldr	w0, [x29, #136]
  400aa0:	7100001f 	cmp	w0, #0x0
  400aa4:	540000ca 	b.ge	400abc <main+0xe0>  // b.tcont
  400aa8:	90000000 	adrp	x0, 400000 <_init-0x648>
  400aac:	91356000 	add	x0, x0, #0xd58
  400ab0:	97ffff10 	bl	4006f0 <puts@plt>
  400ab4:	12800000 	mov	w0, #0xffffffff            	// #-1
  400ab8:	1400004c 	b	400be8 <main+0x20c>
  400abc:	90000000 	adrp	x0, 400000 <_init-0x648>
  400ac0:	91338000 	add	x0, x0, #0xce0
  400ac4:	52800041 	mov	w1, #0x2                   	// #2
  400ac8:	97fffef2 	bl	400690 <open@plt>
  400acc:	b90087a0 	str	w0, [x29, #132]
  400ad0:	b94087a0 	ldr	w0, [x29, #132]
  400ad4:	7100001f 	cmp	w0, #0x0
  400ad8:	540000ca 	b.ge	400af0 <main+0x114>  // b.tcont
  400adc:	90000000 	adrp	x0, 400000 <_init-0x648>
  400ae0:	9135c000 	add	x0, x0, #0xd70
  400ae4:	97ffff03 	bl	4006f0 <puts@plt>
  400ae8:	12800000 	mov	w0, #0xffffffff            	// #-1
  400aec:	1400003f 	b	400be8 <main+0x20c>
  400af0:	9101a3a0 	add	x0, x29, #0x68
  400af4:	aa0003e2 	mov	x2, x0
  400af8:	d28e0121 	mov	x1, #0x7009                	// #28681
  400afc:	f2b00381 	movk	x1, #0x801c, lsl #16
  400b00:	b9408ba0 	ldr	w0, [x29, #136]
  400b04:	97ffff07 	bl	400720 <ioctl@plt>
  400b08:	b9008fa0 	str	w0, [x29, #140]
  400b0c:	b9408fa0 	ldr	w0, [x29, #140]
  400b10:	7100001f 	cmp	w0, #0x0
  400b14:	5400008a 	b.ge	400b24 <main+0x148>  // b.tcont
  400b18:	90000000 	adrp	x0, 400000 <_init-0x648>
  400b1c:	91362000 	add	x0, x0, #0xd88
  400b20:	97fffef4 	bl	4006f0 <puts@plt>
  400b24:	390183bf 	strb	wzr, [x29, #96]
  400b28:	390187bf 	strb	wzr, [x29, #97]
  400b2c:	910183a0 	add	x0, x29, #0x60
  400b30:	aa0003e2 	mov	x2, x0
  400b34:	d28e01a1 	mov	x1, #0x700d                	// #28685
  400b38:	f2b00041 	movk	x1, #0x8002, lsl #16
  400b3c:	b9408ba0 	ldr	w0, [x29, #136]
  400b40:	97fffef8 	bl	400720 <ioctl@plt>
  400b44:	b9008fa0 	str	w0, [x29, #140]
  400b48:	b9408fa0 	ldr	w0, [x29, #140]
  400b4c:	7100001f 	cmp	w0, #0x0
  400b50:	5400008a 	b.ge	400b60 <main+0x184>  // b.tcont
  400b54:	90000000 	adrp	x0, 400000 <_init-0x648>
  400b58:	91362000 	add	x0, x0, #0xd88
  400b5c:	97fffee5 	bl	4006f0 <puts@plt>
  400b60:	9100a3a0 	add	x0, x29, #0x28
  400b64:	aa0003e2 	mov	x2, x0
  400b68:	d28e0121 	mov	x1, #0x7009                	// #28681
  400b6c:	f2b00481 	movk	x1, #0x8024, lsl #16
  400b70:	b94087a0 	ldr	w0, [x29, #132]
  400b74:	97fffeeb 	bl	400720 <ioctl@plt>
  400b78:	b9008fa0 	str	w0, [x29, #140]
  400b7c:	b9408fa0 	ldr	w0, [x29, #140]
  400b80:	7100001f 	cmp	w0, #0x0
  400b84:	5400008a 	b.ge	400b94 <main+0x1b8>  // b.tcont
  400b88:	90000000 	adrp	x0, 400000 <_init-0x648>
  400b8c:	9136a000 	add	x0, x0, #0xda8
  400b90:	97fffed8 	bl	4006f0 <puts@plt>
  400b94:	b94077a1 	ldr	w1, [x29, #116]
  400b98:	b9407ba2 	ldr	w2, [x29, #120]
  400b9c:	b9407fa3 	ldr	w3, [x29, #124]
  400ba0:	394187a0 	ldrb	w0, [x29, #97]
  400ba4:	2a0003e4 	mov	w4, w0
  400ba8:	90000000 	adrp	x0, 400000 <_init-0x648>
  400bac:	91374000 	add	x0, x0, #0xdd0
  400bb0:	97fffed8 	bl	400710 <printf@plt>
  400bb4:	b94033a1 	ldr	w1, [x29, #48]
  400bb8:	b9402fa2 	ldr	w2, [x29, #44]
  400bbc:	b9402ba3 	ldr	w3, [x29, #40]
  400bc0:	90000000 	adrp	x0, 400000 <_init-0x648>
  400bc4:	9137c000 	add	x0, x0, #0xdf0
  400bc8:	97fffed2 	bl	400710 <printf@plt>
  400bcc:	17ffffc9 	b	400af0 <main+0x114>
  400bd0:	f9400ba0 	ldr	x0, [x29, #16]
  400bd4:	f9400001 	ldr	x1, [x0]
  400bd8:	90000000 	adrp	x0, 400000 <_init-0x648>
  400bdc:	91346000 	add	x0, x0, #0xd18
  400be0:	97fffecc 	bl	400710 <printf@plt>
  400be4:	52800000 	mov	w0, #0x0                   	// #0
  400be8:	a8c97bfd 	ldp	x29, x30, [sp], #144
  400bec:	d65f03c0 	ret

0000000000400bf0 <__libc_csu_init>:
  400bf0:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400bf4:	910003fd 	mov	x29, sp
  400bf8:	a901d7f4 	stp	x20, x21, [sp, #24]
  400bfc:	b0000094 	adrp	x20, 411000 <__FRAME_END__+0x101fc>
  400c00:	b0000095 	adrp	x21, 411000 <__FRAME_END__+0x101fc>
  400c04:	91374294 	add	x20, x20, #0xdd0
  400c08:	913722b5 	add	x21, x21, #0xdc8
  400c0c:	a902dff6 	stp	x22, x23, [sp, #40]
  400c10:	cb150294 	sub	x20, x20, x21
  400c14:	f9001ff8 	str	x24, [sp, #56]
  400c18:	2a0003f6 	mov	w22, w0
  400c1c:	aa0103f7 	mov	x23, x1
  400c20:	9343fe94 	asr	x20, x20, #3
  400c24:	aa0203f8 	mov	x24, x2
  400c28:	97fffe88 	bl	400648 <_init>
  400c2c:	b4000194 	cbz	x20, 400c5c <__libc_csu_init+0x6c>
  400c30:	f9000bb3 	str	x19, [x29, #16]
  400c34:	d2800013 	mov	x19, #0x0                   	// #0
  400c38:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400c3c:	aa1803e2 	mov	x2, x24
  400c40:	aa1703e1 	mov	x1, x23
  400c44:	2a1603e0 	mov	w0, w22
  400c48:	91000673 	add	x19, x19, #0x1
  400c4c:	d63f0060 	blr	x3
  400c50:	eb13029f 	cmp	x20, x19
  400c54:	54ffff21 	b.ne	400c38 <__libc_csu_init+0x48>  // b.any
  400c58:	f9400bb3 	ldr	x19, [x29, #16]
  400c5c:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400c60:	a942dff6 	ldp	x22, x23, [sp, #40]
  400c64:	f9401ff8 	ldr	x24, [sp, #56]
  400c68:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400c6c:	d65f03c0 	ret

0000000000400c70 <__libc_csu_fini>:
  400c70:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400c74 <_fini>:
  400c74:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400c78:	910003fd 	mov	x29, sp
  400c7c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400c80:	d65f03c0 	ret
